1. Field of the Invention
The present invention relates to a display element drive apparatus for driving a display element on a display panel of an image display apparatus. More particularly, the present invention relates to a semiconductor circuit technology for causing a display element drive apparatus to operate with high speed.
2. Description of the Prior Art
An image display apparatus comprising a display panel, such as a liquid crystal display panel or the like, is provided with a display element drive apparatus so as to drive a display element on the display panel. As such a display element drive apparatus, for example, a display element drive apparatus 500 illustrated in FIG. 1 is known (e.g., Japanese Unexamined Patent Publication No. H11-249626 (FIG. 2)).
In a display element drive apparatus, a timing of rising of a clock signal is used as a reference and, in addition, a timing of falling of the clock signal is also often used as a reference. Therefore, in the display element drive apparatus 500, clock signals which have opposite phases (signals N1 and N2 described below) are generated.
Specifically, the display element drive apparatus 500 comprises a comparator 501, an inverter 502, a first frequency dividing flop-flop 503, a second frequency dividing flip-flop 504, a delay circuit 505, a first data holding flip-flop 506, and a second data holding flip-flop 507.
The comparator 501 receives clock signals CLKP1 and CLKN1, which are low amplitude differential signals, through a positive-phase input terminal and a negative-phase input terminal thereof, respectively, and outputs a voltage signal (N1) corresponding to a potential difference between CLKP1 and CLKN1. As used herein, the term “low amplitude” means that the amplitude of a signal is small compared to a potential difference between a power source potential and a ground potential of the display element drive apparatus.
The inverter 502 inverts an output of the comparator 501 and outputs the inverted output to the second frequency dividing flip-flop 504.
The first frequency dividing flop-flop 503 frequency-divides the output signal N1 of the comparator 501. Specifically, as illustrated in FIG. 1, an inverted output NQ of the first frequency dividing flop-flop 503 is input to an input D of the first frequency dividing flop-flop 503. As a result, a signal obtained by frequency-dividing the output signal N1 is output from an output Q of the first frequency dividing flop-flop 503 at a timing of rising of the output signal N1 of the comparator 501. The output Q of the first frequency dividing flop-flop 503 is input to a clock CP of the first data holding flip-flop 506, and is used as a timing signal in the display element drive apparatus 500.
The second frequency dividing flip-flop 504 frequency-divides an output signal N2 of the inverter 502. Specifically, as illustrated in FIG. 1, an inverted output NQ of the second frequency dividing flip-flop 504 is input to an input D of the second frequency dividing flip-flop 504. As a result, a signal obtained by frequency-dividing the output signal N1 is output from an output Q of the second frequency dividing flip-flop 504 at a timing of falling of the output signal N1 of the comparator 501. The output Q of the second frequency dividing flip-flop 504 is used as a timing signal in the display element drive apparatus 500 as well as the output Q of the first frequency dividing flop-flop 503. Thus, in the display element drive apparatus 500, the timing of falling of the output signal N1 is used as an operation reference in addition to the timing of rising of the output signal N1.
The delay circuit 505 outputs an input data signal D1, which is obtained by delaying an input data signal DATA1, to the first data holding flip-flop 506 and the second data holding flip-flop 507. The delay circuit 505 is used to adjust a timing between the clock signal (the output Q), which is output by the first frequency dividing flop-flop 503 or the second frequency dividing flip-flop 504, and the input data signal DATA1.
The first data holding flip-flop 506 holds the input data signal D1 output by the delay circuit 505 at a rising edge of the output Q of the first frequency dividing flop-flop 503.
The second data holding flip-flop 507 holds the input data signal D1 output by the delay circuit 505 at a rising edge of the output Q of the second frequency dividing flip-flop 504. In other words, the first data holding flip-flop 506 and the second data holding flip-flop 507 have different timings of holding the input data signal D1.
However, in the conventional display element drive apparatus 500, the duty ratio of the output signal N1 of the comparator 501 may be significantly deteriorated, depending on conditions, such as frequency, power source voltage, process, and temperature.
If the duty ratio of the output signal N1 of the comparator 501 is significantly deteriorated, a relationship in phase between the output Q of the first frequency dividing flop-flop 503 and the output Q of the second frequency dividing flip-flop 504 is significantly deteriorated, so that there is a possibility that the first data holding flip-flop 506 and the second data holding flip-flop 507 cannot receive the output D1 of the delay circuit 505. Particularly, for example, when the display element drive apparatus operates with high speed, an erroneous operation is likely to occur.
Hereinafter, a change in each signal during an operation of the display element drive apparatus 500 will be described with reference to a timing chart of FIG. 2.
In the example, as illustrated in FIG. 2, the timing of rising of the output signal N1 of the comparator 501 is delayed by a delay time T1 from the timing of rising of the clock signal CLKP1. The timing of rising of the output signal N1 is also delayed by a delay time T2 from the timing of falling of the clock signal CLKP1.
In this case, a total delay time TS1 of rising of the output signal of the first frequency dividing flop-flop 503 is represented by:total delay time TS1=(delay time T1+delay time T3)where the delay time T3 is a delay time of the first frequency dividing flop-flop 503 itself.
Also, a total delay time TS2 of rising of the output signal of the second frequency dividing flip-flop 504 is represented by:total delay time TS2=(delay time T2+delay time T4+delay time T5)where the delay time T4 is a delay time from when a signal is input to the inverter 502 to when the signal is output therefrom, and the delay time T5 is a delay time of the second frequency dividing flip-flop 504 itself.
In this case, if characteristics of the comparator 501 are changed, depending on conditions, such as frequency, power source voltage, process, and temperature, the delay time T1 is not equal to the delay time T2. As a result, the duty ratio (a ratio of a HIGH interval and a LOW interval) of the output signal N1 of the comparator 501 is deviated. Also, characteristics of the inverter 502 are changed, depending on conditions, such as frequency, power source voltage, process, and temperature, so that the delay time T4 from the input to the output of the inverter 502 is changed. Therefore, a significant difference is expected between the total delay time TS1 and the total delay time TS2.
Here, a setup time and a hold time for a HIGH level of the input data signal DATA1 are represented by S1 and H1, respectively. A delay time of rising of the input data signal D1 is represented by T6. A delay time of falling of the input data signal D1 is represented by T7. In this case, the total delay time TS1 is substantially equal to or larger than the delay time T6. Therefore, the first data holding flip-flop 506 can hold HIGH-level data (the input data signal D1).
On the other hand, the total delay time TS2 may be larger than a delay time which is a sum of the delay time T7 and the hold time H1. Therefore, in this case, the second data holding flip-flop 507 cannot hold HIGH-level data (the input data signal D1).
As described above, in the conventional display element drive apparatus 500, when the timing of falling as well as the timing of rising of a clock signal are used as references so as to receive data in an internal circuit, data may not be correctly received. It is expected that this problem becomes more significant, as the operating speed of the display element drive apparatus 500 is increased.